This invention relates generally to read-only memories, and more particularly, to read-only memories fabricated in monolithic form. A read-only memory, or ROM, is one in which information is stored permanently, even when power is not applied to the device. The stored information in a ROM may not be conveniently changed. In other words, information may be read from the memory but not conveniently written into it. Read-only memories are widely used in digital computers and other equipment, for the storage of frequently used programs and data.
In an electronic ROM, digital information is stored in the form of selectively made electrode contacts at the storage locations of a plurality of binary digits, or bits. The bit storage locations are typically at row and column intersections of an addressable electrical matrix table or array. A binary one or zero is stored by either making or not making an electrical contact between conducting media defining the rows and columns of the array. Specifically, the selective contacts may be made by etching holes at selected locations in an oxide layer, to establish the desired connections. However, the invention to be described is not limited to any particular technique for selectively storing information in a read-only memory.
Information in a read-only memory is retrieved by energizing a selected row line and a selected column line. A sense amplifier can then detect whether or not there is electrical contact at the selected row and column intersection, and this is read as either a binary one or a binary zero. If the information to be stored is in the nature of random data, half of the bit storage locations will be coded as ones and the remainder as zeros. Since random data storage is likely to be an exceptional case, there will often be situations in which a majority of selected contacts are made at the available bit locations. The electrical capacitance or loading of the memory device is a direct function of the number of bit locations programmed. Thus, for a given power applied to a row or column, the circuit delay will be a direct function of the number of bit locations in the row or column that have been programmed for electrical contact. Conversely, for a given circuit delay or access time, the required power for a row or colun will depend directly on the number of bit locations programmed for electrical contact.
Given that the memory must be designed to operate at a specified maximum access time, the worst case from the standpoint of power consumption is a row and column combination having all the bit locations programmed to make electrical contact. Ideally, if the circuit designer knew in advance which rows and columns would be subject to heavy loading, the power supplies connected to those rows and columns could be appropriately designed to meet the access time requirements. Unfortunately, read-only memory circuits are usually designed for general-purpose use, and the designer is unaware of the form of the information to be stored in the circuit. Accordingly, the circuit must be designed to handle the worst-case loading condition for all row and column combinations. The power supply circuits for the memory must therefore be designed to provide power at a level that will in many instances be unnecessarily high.
Another way of stating this problem is that the "speed-power" product of the device is unnecessarily high. The speed-power product, or more precisely, the product of operation time and power, is a commonly encountered measure of the efficiency of monolithic circuits. In read-only memories, the speed-power product is higher than it would need to be if all row and column circuits did not have to be designed for the worst-case loading condition.
From the foregoing, it will be appreciated that there is a need for a read-only memory device that avoids having to provide a power supply for the worst-case loading condition in every row and column of the memory circuit. The present invention fulfills this need.